Synopsys Powers World's Fastest UCIe-Based Multi-Die Designs With New IP Operating at 40 Gbps
Synopsys Powers World's Fastest UCIe-Based Multi-Die Designs With New IP Operating at 40 Gbps
"Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications," said Complete Synopsys 40G UCIe IP Solution Delivers Maximum Bandwidth for Die-to-Die Connectivity in High-Performance AI Data Center Chips
完整的新思科技 40G UCiE IP 解决方案为高性能 AI 数据中心芯片中的裸片连接提供最大带宽
Highlights
亮点
- Industry's first complete 40G UCIe IP solution, including controller, PHY, and verification IP, enables fast connectivity between heterogeneous and homogeneous dies
- Synopsys 40G UCIe PHY IP offers 25% higher bandwidth than the UCIe specification without impact on energy efficiency and silicon footprint
- Integrated signal integrity monitors and testability features improve multi-die package reliability and enable in-field monitoring throughout the silicon lifecycle
- Synopsys 40G UCIe IP is built on a silicon-proven architecture with interoperability success in multiple advanced foundry processes
- 业界首款完整的 40G UCie IP 解决方案，包括控制器、PHY 和验证 IP，可实现异构和同构芯片之间的快速连接
- 新思科技 40G UCiE PHY IP 提供的带宽比 UCie 规格高 25%，而不会影响能效和硅占用量
- 集成的信号完整性监视器和可测试性功能提高了多芯片封装的可靠性，并在整个硅生命周期中实现现场监控
- Synopsys 40G UCiE IP 建立在经过硅验证的架构之上，在多个高级铸造工艺中成功实现了互操作性
SUNNYVALE, Calif., Sept. 9, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete UCIe IP solution operating at up to 40 Gbps per pin to address the increased compute performance requirements of the world's fastest AI data centers. The UCIe interconnect, the de facto standard for die-to-die connectivity, is critical for high-bandwidth, low-latency die-to-die connectivity in multi-die packages, enabling more data to travel efficiently across heterogeneous and homogeneous dies, or chiplets, in today's AI data center systems. Synopsys' 40G UCIe IP supports both organic substrate and high-density, advanced packaging technologies to give designers the flexibility to explore the packaging options that best fit their needs. The complete Synopsys 40G UCIe IP solution, including PHY, controller, and verification IP, is a key component of Synopsys' comprehensive and scalable multi-die solution for fast heterogeneous integration from early architecture exploration to manufacturing.
加利福尼亚州森尼韦尔，2024年9月9日 /PRNewswire/--新思科技公司（纳斯达克股票代码：SNPS）今天宣布推出业界首款完整的UCie IP解决方案，每引脚运行速度高达40 Gbps，以满足世界上最快的人工智能数据中心不断提高的计算性能要求。UCie 互连是事实上的晶片对芯片连接标准，对于多芯片封装中的高带宽、低延迟的芯片对芯片连接至关重要，它使更多数据能够在当今的人工智能数据中心系统中的异构和同构芯片或小芯片之间高效传输。新思科技的40G UCiE IP支持有机基板和高密度的先进封装技术，使设计人员能够灵活地探索最适合其需求的封装选项。完整的新思科技 40G UCie IP 解决方案，包括 PHY、控制器和验证 IP，是新思科技全面且可扩展的多芯片解决方案的关键组件，用于从早期架构探索到制造的快速异构集成。
"Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications," said Jongwoo Lee, vice president of the System LSI IP Development Team at Samsung Electronics. "Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow's high-performance data centers."
三星电子System LSI IP开发团队副总裁Jongwoo Lee表示：“异构集成与高带宽的芯片间连接使我们有机会提供具有数据密集型人工智能应用所需效率的新存储器芯片。”“利用新思科技的全新40G UCiE IP，我们可以扩大合作范围，为未来的高性能数据中心开发行业领先的小芯片解决方案。”
"Launching the industry's first complete 40G UCIe IP solution underscores Synopsys' continued investment in advancing semiconductor innovation," said Michael Posner, vice president of IP product management at Synopsys. "Our active contribution to the UCIe consortium has enabled us to deliver a robust UCIe solution that helps our customers successfully develop and optimize their multi-die designs for high-performance AI computing systems."
新思科技IP产品管理副总裁迈克尔·波斯纳表示：“推出业界首个完整的40G UCiE IP解决方案凸显了新思科技对推进半导体创新的持续投资。”“我们对UCie联盟的积极贡献使我们能够提供强大的UCiE解决方案，帮助我们的客户成功开发和优化高性能人工智能计算系统的多芯片设计。”
Advanced capabilities of the new Synopsys 40G UCIe IP solution include:
新思科技 40G UCie IP 解决方案的高级功能包括：
- Simplified Solution Eases IP Integration: Single reference clock feature simplifies the clocking architecture and optimizes power. For ease of use and integration, the IP speeds-up die-to-die link initialization without the need to load the firmware.
- Silicon Health Monitoring Enhances Multi-Die Package Reliability: To ensure reliability at the die, die-to-die, and multi-die package levels, Synopsys 40G UCIe IP offers test and silicon lifecycle management (SLM) features. The monitoring, test, and repair IP and integrated signal integrity monitors enable diagnosis and analysis of the multi-die package from in-design to in-field.
- Successful Ecosystem Interoperability: For on-chip interconnect needs of the latest CPUs and GPUs, Synopsys 40G UCIe IP supports the most popular on-chip interconnect fabrics including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. For successful interoperability, the IP is compliant with the UCIe 1.1 and 2.0 standards, which Synopsys helps to develop and promote as an active member of the UCIe Consortium.
- Pre-Verified Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, is used in Synopsys' pre-verified design reference flow that includes all the required design collateral such as automated routing flow, interposer studies, and signal integrity analysis.
- Broad IP Solutions for Multi-Die Designs: In addition to UCIe IP and high-speed SerDes, Synopsys offers HBM3 and 3DIO IP to enable high-capacity memory and 3D packaging.
- 简化的解决方案简化了 IP 集成：单参考时钟功能简化了时钟架构并优化了功耗。为了便于使用和集成，IP 无需加载固件即可加快死对芯链路的初始化。
- 硅健康监控增强了多芯片封装的可靠性：为确保芯片、芯片到芯片和多芯片封装级别的可靠性，Synopsys 40G UCie IP 提供测试和硅生命周期管理 (SLM) 功能。监控、测试和修复 IP 和集成的信号完整性监视器支持从设计到现场对多芯片封装进行诊断和分析。
- 成功的生态系统互操作性：针对最新 CPU 和 GPU 的片上互连需求，新思科技 40G UCie IP 支持最受欢迎的片上互连架构，包括 AXI、CHI 芯片对芯片、流媒体、PCI Express 和 CXL。为了成功实现互操作性，该IP符合UCie 1.1和2.0标准，作为UCie联盟的活跃成员，新思科技帮助开发和推广了这些标准。
- 预先验证的设计参考流程：Synopsys UCie IP和Synopsys 3DIC Compiler（一个统一的探索到签核平台）的组合用于新思科技的预验证设计参考流程，其中包括所有必需的设计资料，例如自动布线流程、中介层研究和信号完整性分析。
- 适用于多晶片设计的广泛IP解决方案：除了UCiE IP和高速SerDes之外，新思科技还提供HBM3和3DIO IP，以支持高容量存储器和三维封装。
Availability & Additional Resources
可用性和其他资源
The Synopsys 40G UCIe IP will be available in late 2024 for multiple foundries and processes.
新思科技40G UCiE IP将于2024年底上市，适用于多个铸造厂和工艺。
- Web: Synopsys UCIe IP Solution
- Blog: Synopsys Introduces Industry's First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
- Blog: UCIe 2.0 - Setting the Tone for Chiplet Interoperability
- 网页：新思科技 UCie IP 解决方案
- 博客：新思科技推出业界首款40G UCiE IP解决方案，为高性能多芯片设计提供支持
- 博客：UCie 2.0-为 Chiplet 互操作性设定基调
About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at .
关于 Synopsys
Synopsys, Inc.（纳斯达克股票代码：SNPS）提供可信且全面的硅到系统设计解决方案，从电子设计自动化到硅 IP 和系统验证与验证，推动智能无处不在的时代。我们与各行各业的半导体和系统客户密切合作，最大限度地提高他们的研发能力和生产力，推动当今的创新，点燃未来的独创性。要了解更多信息，请访问。
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SOURCE Synopsys, Inc.
来源 Synopsys, Inc.
