HONG KONG, Dec. 26, 2024 /PRNewswire/ -- Nano Labs Ltd (Nasdaq: NA) ("we," the "Company," or "Nano Labs"), a leading fabless integrated circuit design company and product solution provider in China, today announced the launch of FPU3.0, an ASIC architecture designed to enhance artificial intelligence (AI) inference and blockchain performance. Featuring advanced 3D DRAM stacking technology, FPU3.0 delivers a fivefold boost in power efficiency over the previous FPU2.0 architecture, setting a new standard for energy-efficient, high-performance ASICs. This latest advancement highlights the Company's robust research and development capabilities in adopting cutting-edge technologies and its commitment to driving innovation and widespread adoption in the AI and cryptocurrency industry.
The FPU series represents Nano Labs' proprietary set of ASIC chip design architectures, purpose-built for high-bandwidth High Throughput Computing (HTC) applications. Such ASIC chips are optimized for specific functions or applications, typically delivering lower power consumption and higher computational efficiency than general-purpose CPUs and GP-GPUs. These ASICs are increasingly utilized in AI inference, edge AI computing, data transmission processing under 5G networks, network acceleration, and more.
The Nano FPU architecture comprises four fundamental modules and IPs: the Smart NOC (Network-on-Chip), the high-bandwidth memory controller, the chip-to-chip interconnect IOs, and the FPU core. This modular provides remarkable flexibility, enabling rapid product iteration by updating the FPU core IP while reusing or upgrading other IPs and modules as needed - often sufficient to introduce new features.
Notably, the FPU3.0 architecture incorporates stacked 3D memory with a theoretical bandwidth of 24TB/s and an upgraded Smart-NOC on-chip network. This network supports a mix of large and small compute cores, full-crossbar, and feed-through traffic types on the bus. The FPU3.0 architecture holds the potentials to excel in various fields, delivering superior performance, lower power consumption, and faster product iteration cycles.
About Nano Labs Ltd
Nano Labs Ltd is a leading fabless integrated circuit ("IC") design company and product solution provider in China. Nano Labs is committed to the development of high throughput computing ("HTC") chips, high performance computing ("HPC") chips, distributed computing and storage solutions, smart network interface cards ("NICs") vision computing chips and distributed rendering. Nano Labs has built a comprehensive flow processing unit ("FPU") architecture which offers solution that integrates the features of both HTC and HPC. Nano Lab's Cuckoo series are one of the first near-memory HTC chips available in the market*. For more information, please visit the Company's website at: ir.nano.cn.
* According to an industry report prepared by Frost & Sullivan.
SOURCE Nano Labs Ltd
香港,2024 年 12 月 26 日 /PRNewswire/--中國領先的無晶圓廠集成電路設計公司和產品解決方案供應商納米實驗室有限公司(納斯達克股票代碼:NA)(「我們」,「公司」 或 「納米實驗室」)今天宣佈推出FPU3.0,這是一款旨在增強人工智能(AI)推理和區塊鏈性能的ASIC架構。FPU3.0採用先進的3D DRAM堆疊技術,與之前的FPU2.0架構相比,能效提高了五倍,爲高能效、高性能的ASIC樹立了新的標準。這一最新進展凸顯了該公司在採用尖端技術方面的強大研發能力,以及其對推動人工智能和加密貨幣行業創新和廣泛採用的承諾。
FPU 系列代表了 Nano Labs 專有的 ASIC 芯片設計架構,專爲高帶寬高吞吐量計算 (HTC) 應用而構建。此類 ASIC 芯片針對特定功能或應用進行了優化,與通用 CPU 和 GP-GPU 相比,通常能提供更低的功耗和更高的計算效率。這些 ASIC 越來越多地用於人工智能推理、邊緣 AI 計算、5G 網絡下的數據傳輸處理、網絡加速等。
Nano FPU 架構包括四個基本模塊和 IP:智能 NOC(片上網絡)、高帶寬內存控制器、芯片間互連 IO 和 FPU 內核。該模塊化提供了非凡的靈活性,通過更新 FPU 核心 IP 實現快速產品迭代,同時根據需要重複使用或升級其他 IP 和模塊,通常足以引入新功能。
值得注意的是,FPU3.0架構採用了理論帶寬爲24Tb/s的堆疊式3D內存和升級後的Smart-NOC片上網絡。該網絡支持總線上混合使用大型和小型計算內核、全橫樑和直通流量類型。FPU3.0 架構具有在各個領域脫穎而出的潛力,可提供卓越的性能、更低的功耗和更快的產品迭代週期。
關於毫微實驗室有限公司
毫微實驗室有限公司是中國領先的無晶圓廠集成電路(「IC」)設計公司和產品解決方案供應商。毫微實驗室致力於開發高吞吐量計算(「HTC」)芯片、高性能計算(「HPC」)芯片、分佈式計算和存儲解決方案、智能網絡接口卡(「NIC」)視覺計算芯片和分佈式渲染。毫微實驗室已經建立了綜合流量處理單元(「FPU」)架構,該架構提供的解決方案集成了HTC和HPC的功能。Nano Lab的Cuckoo系列是市場上首批近內存的HTC芯片之一*。欲了解更多信息,請訪問該公司的網站:ir.nano.cn。
*根據弗羅斯特沙利文編寫的行業報告。
來源 Nano Labs Ltd