Synopsys and TSMC Streamline Multi-Die System Complexity With Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process
Synopsys and TSMC Streamline Multi-Die System Complexity With Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process
Comprehensive Multi-Die System Design Solution Supports 3Dblox 2.0 Standard and TSMC 3DFabricTM Technologies to Boost Productivity for Fast Heterogeneous Integration
全面的多芯片系统设计解决方案支持 3Dblox 2.0 标准版和台积电 3DFabricTM 提高生产力的技术，实现快速异构集成
Highlights:
亮点：
- Synopsys 3DIC Compiler integrates with 3Dblox 2.0 standard for heterogeneous integration and a complete exploration-to-signoff solution.
- Synopsys UCIe PHY IP, which achieved first-pass silicon success on TSMC N3E process, provides low-latency, low-power, and high-bandwidth die-to-die connectivity.
- The combination of UCIe PHY IP and 3DIC Compiler optimizes multi-die system design for higher quality-of-results with minimal integration risk.
- Synopsys 3DIC Compiler 与 3Dblox 2.0 标准集成，用于异构集成和完整的探索到签核解决方案。
- Synopsys uCie PHY IP 在台积电 N3E 工艺上取得了首次通过芯片的成功，它提供了低延迟、低功耗和高带宽的裸片到芯片连接。
- UCie PHY IP 和 3DIC Compiler 的组合优化了多芯片系统设计，以最小的集成风险实现更高的结果质量。
SUNNYVALE, Calif., Sept. 27, 2023 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.
加利福尼亚州桑尼维尔， 2023年9月27日 /PRNewswire/ — Synopsys, Inc.（纳斯达克股票代码：SNPS）今天宣布，它将扩大与台积电的合作，通过支持最新的3Dblox 2.0标准和台积电的3DFabric技术的全面解决方案来推进多芯片系统的设计。Synopsys Multi-Die System 解决方案包括 3DIC Compiler，这是一个统一的探索到签核平台，可在容量和性能方面提供最高水平的设计效率。此外，Synopsys在台积电领先的N3E工艺上实现了芯片到芯片的无缝连接，其通用Chiplet互联快速（UCiE）IP取得了首次芯片成功。
"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."
台积电设计基础设施管理部负责人Dan Kochpatcharin表示：“台积电一直在与新思科技密切合作，提供差异化的解决方案，以应对设计师从早期架构到制造的最复杂的挑战。”“我们与Synopsys的长期合作历史使我们共同的客户受益于性能和能效优化的解决方案，帮助他们满足高性能计算、数据中心和汽车应用的多芯片系统设计要求。”
"Through our strong alliance with TSMC, we provide a comprehensive and scalable solution for unprecedented performance and efficiency in multi-die system designs," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "The ability to explore, analyze, and signoff multi-die system designs in a unified platform using a common standard like 3Dblox 2.0, along with the silicon proof of the Synopsys UCIe PHY IP on the TSMC N3E process, enables customers to accelerate system design from early architecture all the way to manufacturing."
他说：“通过与台积电的强大联盟，我们提供了全面且可扩展的解决方案，在多芯片系统设计中实现前所未有的性能和效率。” 桑杰巴厘岛，新思科技EDA集团战略和产品管理副总裁。“能够使用3Dblox 2.0等通用标准在统一平台上探索、分析和签署多芯片系统设计，再加上台积电N3E流程上Synopsys uCie PHY IP的硅验证，使客户能够加快从早期架构到制造的系统设计。”
Synopsys 3DIC Compiler, certified by TSMC, enables full-stack designs using the 3Dblox 2.0 standard and 3DFabric technologies in a unified die/package exploration, co-design, and analysis platform. Its integrated system analysis capability allows co-optimization of thermal and power integrity aligned with 3Dblox 2.0 system prototyping, which helps to ensure design feasibility. Synopsys and Ansys continue to collaborate and deliver signoff accuracy for system-level effects with the integration of Synopsys 3DIC Compiler and Ansys multi-physics analysis technologies. Synopsys 3DIC Compiler also interoperates with the Synopsys Test products to ensure volume test and quality.
通过台积电认证的 Synopsys 3DIC Compiler 可在统一的模具/封装探索、协同设计和分析平台中使用 3Dblox 2.0 标准和 3DFabric 技术实现全栈设计。其集成的系统分析功能可实现与 3Dblox 2.0 系统原型设计相一致的散热和电源完整性协同优化，这有助于确保设计的可行性。通过集成新思科技3DIC编译器和Ansys多物理场分析技术，Synopsys和Ansys继续合作，为系统级效果提供签核精度。Synopsys 3DIC Compiler 还与 Synopsys Test 产品互操作，以确保批量测试和质量。
Adopted by multiple leading companies, Synopsys' UCIe PHY IP on the TSMC N3E process has achieved first-pass silicon success, helping designers efficiently integrate the de facto standard for die-to-die connectivity into their multi-die systems. The results demonstrate maximum power efficiency and performance at 16Gbps, scalable to 24Gbps, with robust link margins. Supporting standard and advanced packaging, Synopsys' complete UCIe controller, PHY and verification IP solution offers test, repair, and monitoring capabilities to help ensure multi-die system reliability even during in-field operation. In addition, Synopsys provides a complete IP solution for HBM3 to address the high memory bandwidth requirements of multi-die systems. The combination of Synopsys IP and Synopsys 3DIC Compiler enables higher productivity and lowers IP integration risk by automating routing, interposer studies, and signal integrity analysis in support of the 3Dblox 2.0 die-to-die feasibility studies.
Synopsys在台积电N3E工艺上的UCie PHY IP已被多家领先公司采用，取得了首次通过芯片的成功，帮助设计人员高效地将模具到芯片连接的事实标准集成到他们的多芯片系统中。结果表明，在16Gbps时具有最高的能效和性能，可扩展到24Gbps，并具有稳健的链路余量。Synopsys的完整UCie控制器、PHY和验证IP解决方案支持标准和高级封装，提供测试、修复和监控功能，即使在现场操作期间也能帮助确保多芯片系统的可靠性。此外，Synopsys为HBM3提供了完整的IP解决方案，以满足多芯片系统的高内存带宽要求。Synopsys IP 和 Synopsys 3DIC Compiler 的组合通过自动布线、中介器研究和信号完整性分析来支持3Dblox 2.0 die-to-die可行性研究，从而提高生产率并降低IP集成风险。
Availability
可用性
- Synopsys UCIe PHY IP on the TSMC N3E process and 3DIC Compiler are available now.
- Synopsys HBM3 IP is available on advanced TSMC processes.
- 台积电 N3E 工艺上的 Synopsys uCie PHY IP 和 3DIC Compiler 现已上市。
- Synopsys HBM3 IP 可用于台积电的高级工艺。
Additional Resources
其他资源
- Web: Synopsys Multi-Die System solution
- Synopsys Industry Insight Report: How Quickly Will Multi-Die Systems Change Semiconductor Design?
- Webinars: Requirements for Multi-Die System Success
- Web: Industry's Broadest IP Portfolio for TSMC N3E Achieves First-Pass Silicon Success
- 网页：新思科技多芯片系统解决方案
- Synopsys 行业洞察报告：多芯片系统将以多快的速度改变半导体设计？
- 网络研讨会：多芯片系统成功的必要条件
- 网页：业界最广泛的台积电 N3E IP 产品组合实现首次芯片成功
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at .
关于 Synopsys
Synopsys, Inc.（纳斯达克股票代码：SNPS）是开发我们每天依赖的电子产品和软件应用程序的创新公司的 Silicon to Software 合作伙伴。作为一家标准普尔500指数公司，Synopsys长期以来一直是电子设计自动化 (EDA) 和半导体IP领域的全球领导者，并提供业界最广泛的应用安全测试工具和服务组合。无论您是创建先进半导体的片上系统 (SoC) 设计人员，还是编写更安全、更高质量代码的软件开发人员，Synopsys 都能提供交付创新产品所需的解决方案。要了解更多信息，请访问。
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Synopsys, Inc.
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SOURCE Synopsys, Inc.
来源 Synopsys, Inc.