Advanced packaging is mainly accomplished by using key interconnection and packaging substrates with advanced design concepts and integration processes to conduct package-level restructuring of chips, which can effectively improve the high functional density packaging of systems, including chip-scale packaging, wafer-level packaging, 2.5D packaging, 3D packaging, among others. According to Yole's prediction, the global advanced packaging market size may reach $48.2 billion in 2026, with a CAGR of approximately 8% from 2021 to 2026, which will contribute the main increment to the global packaging and testing market.

Related symbols: Kingsemi Co., Ltd. (688037.SH) (adhesive development and wet process equipment and bonding machines), Advanced Micro-fabrication Equipment Inc. China (688012.SH) (etching equipment), Tojing Technology (688072.SH) (bonding equipment) and so on.

天風証券の主な見解は次のとおりです：

Packaging technology is divided into traditional packaging and advanced packaging, and there is no clear replacement relationship between the two technologies.

Traditional packaging: It has the advantages of high cost-effectiveness, strong product versatility, low use cost, and wide application fields;

Advanced packaging: Mainly accomplished by using key interconnection and packaging substrates with advanced design concepts and integration processes to conduct package-level restructuring of chips, which can effectively improve the high functional density packaging of systems, including chip-scale packaging, wafer-level packaging, 2.5D packaging, 3D packaging, among others. According to Yole's prediction, the global advanced packaging market size may reach $48.2 billion in 2026, with a CAGR of approximately 8% from 2021 to 2026, which will contribute the main increment to the global packaging and testing market.

Four elements of advanced packaging: RDL, TSV, Bump, and Wafer.

Having any of these elements is called advanced packaging. Among the four elements of advanced packaging, RDL plays the role of XY plane electrical extension, TSV plays the role of Z-axis electrical extension, Bump plays the role of interface interconnection and stress buffering, and Wafer serves as the carrier of the integrated circuit and the medium and carrier of RDL and TSV.

Wafer-level packaging: Fan-in & Fan-out & technology extension.

Wafer-level packaging refers to the process before wafer cutting, and all processes are processed on the wafer. The five basic processes of wafer-level packaging include photolithography, sputtering, electroplating, PR stripping, and metal etching.

2.5D/3D packaging:

2.5D packaging: The integration density is higher than 2D but lower than 3D. In the field of advanced packaging, it specifically refers to the interposer integration method. Currently, the interposer is mostly made of silicon material (mature technology and high-density interconnection characteristics). TSV is almost indispensable in high-density interconnection, and interposer TSV is called 2.5TSV.

3D packaging: Refers to high-density interconnection of chips directly through TSV. The TSV directly produced on the chip is called 3DTSV. The chips are close to each other, and the delay is less. In addition, shortening the length of interconnection can reduce parasitic effects related to speed and convert to performance improvement, thereby largely reducing costs.

リスキーワーニング：

Risks related to industry technological progress, debt repayment, supply and price fluctuation of raw materials, among others.